Write Amplification Reduction for Flash Memory SSDs

Write ampli€cation is an undesirable phenomenon with ƒash memory based SSDs, which not only reduces endurance of ƒash memory, but also imposes write performance penalty on SSDs. Œis paper discusses how to eliminate or reduce the write ampli€cation of SSD interface presenting ƒash memory as a linear array of updatable sectors so that SSD’s performance and endurance can be both improved greatly. A workload, called IRR, is identi€ed which can lead to zero write ampli€cation with a simple data layout manager and a garbage collector implemented in the FTL of SSD. Œe paper then proposes a workload decomposition algorithm which can decompose a general workload into sub-workloads with the IRR property to be stored in di‚erent regions in ƒash memory so that write ampli€cations of the whole workload can be minimized. Extensive simulation results on various o„ine workloads have validated the workload decomposition algorithm’s e‚ectiveness in reducing write ampli€cations. Œe paper also proposes a practical online region-hint decomposition algorithm by employing a generalized data layout manager at the FTL to reduce write ampli€cations. We envision the concepts and results presented in this paper to be guidelines for design and implementation of future €le system and FTL for SSDs where applications can pass workload knowledge and prediction to FTL so that write ampli€cation can be minimized.